The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In conventional processes, an anti-punch through (APT) ion implantation is performed through FinFET fin elements to prevent punch through of FinFET source/drain depletion regions. However, ion implantation of dopants (e.g., dopants used for APT implants) through fins of FinFET devices directly contributes to the formation of defects and the introduction of impurities in a FinFET channel region. Such channel defects and impurities can cause scattering of carriers flowing through the FinFET channel, thus degrading channel mobility and adversely affecting device performance. Dopant implantation through FinFET fins may also result in a non-uniform doping profile, which among other issues can cause variability of FinFET device parameters. Thus, existing techniques have not proved entirely satisfactory in all respects.